1. Field of the Invention
The present invention relates to a semiconductor device capable of improving access efficiency of a semiconductor memory such as a DRAM in particular.
2. Description of Related Art
As a technology to miniaturize and highly-integrate a semiconductor integrated circuit develops, memories such as DRAMs (dynamic random access memory) and SRAMs (static random access memory) become to have larger capacities. However, since miniaturization of a semiconductor has a limit, there is a demand to introduce a new technology to realize a larger capacity. As such a technology, a three-dimensional semiconductor in which semiconductor chips are stacked has been proposed.
Japanese Patent Application Laid-Open No. 4-196263 (Patent Document 1) discloses a measure to realize a large-scale integrated circuit by laminating semiconductor chips so as not to change the chip area, in which memory circuits are integrated on another chip stacked on the main body of the semiconductor integrated circuit. Japanese Patent Applications Laid-Open No. 2002-26283 (Patent Document 2), No. 2003-209222 (Patent Document 3), and No. 2006-13337 (Patent Document 4) disclose a multilayered memory structure in which memory cell arrays are multilayered to realize a larger capacity.
Patent Document 2 describes a multilayered memory chip in which memory peripheral circuits are not provided to the respective chips but are integrated on one chip so that the regions of the peripheral circuits occupied in the chip area are reduced. Patent Document 3 describes an invention in which after a multilayered memory device is manufactured, the memory layers are screened, so that defective memory layers can be eliminated. Patent Document 4 describes an invention in which the input-output bit structure of a stacked memory is reconstructed by changing the data bus wiring combination.
In each of the stacked-type memory devices described above, it is possible to increase the memory capacity in a limited chip area, but none of them describe how to perform data transfer effectively. Further, as a processor linked to a memory becomes to have higher performance, a memory device is required to have not only larger capacity but also an improvement in transfer efficiency of memory data.
In a general purpose DRAM memory chip, a data bus which is a global wire in the chip surface is shared by banks as shown in FIG. 18, and is a bidirectional bus used for both write data and read data. Therefore, in order to prevent collision of write data and read data on a data bus, a waiting time of several cycles is required between a read command and a write command not only for the case of the same bank but also for the case of different banks. This causes a drop in data transfer efficiency between a processor and a DRAM memory, so there is a need to suspend data processing in the processor. This problem is also caused in the case where a plurality of devices in which DRAM chips are packaged are arranged on a board to share a bus, as shown in FIG. 19.
In order to prevent this problem, a semiconductor memory may be configured such that an input unit for write data and an output unit for read data are provided separately, and respective banks share data buses which are separated for write data and read data. Thereby, write data and read data pass different buses, so no waiting time is needed between a read command and a write command.
However, with such a configuration in which data buses for read data and write data are provided separately, the number of wires for data doubles. In the case of a memory device in which chips are stacked, a via wire which is a wire penetrating chips is used for inter-chip wiring, but the diameter of the wire is 20 μm, which is larger than that of an in-plane wire by a digit or more, because the via wire is so formed that an aperture penetrating up to about 50 μm thick of a chip thin film is made and a conductor for wiring is filled in. Therefore, it is impossible to form a large number of via wires in a limited area, so it is desired to use a common data bus for both write data and read data so as to reduce the density of via wires.